1. Field of the Invention
The present invention relates to an integrated circuit multi-chip package, and more particularly, to an integrated circuit multi-chip package and an integrated circuit device, in which an input signal input to one chip from an external source is transmitted to another chip.
2. Description of the Related Art
Operating speed and storage capacity of integrated circuits, such as semiconductor memory circuits, continues to increase at a dramatic pace. Along with this, the importance of package structure to the performance of an integrated circuit has steadily grown. In particular, a technique for effectively arranging and routing bonding pads considerably affects the performance of an integrated circuit. In general, in order to increase the performance of an integrated circuit device, a process known as multi-chip packaging is performed, wherein two or more integrated circuits are stacked and then packaged together.
FIG. 1 is a cross-sectional view of a conventional integrated circuit multi-chip package 10, and FIG. 2 is a plan view of the conventional integrated circuit multi-chip package 10. Referring to FIGS. 1 and 2, two or more chips, e.g., first and second chips 11 and 12, are stacked in the conventional integrated circuit multi-chip package 10, and pads on the chips 11 and 12 are electrically connected to bonding fingers 13 formed on a printed circuit board (PCB) substrate 16 by bonding wires 14. The bonding fingers 13 are electrically connected to external pins 15 via the PCB substrate 16.
The conventional integrated circuit multi-chip package 10 has a ‘direct access’ structure in which a signal is directly input to each chip stacked therein. In other words, pads of the first chip 11 are electrically connected to their respective external pins 15 so that they can receive signals from or transmit signals to their respective external pins 15. Likewise, pads of the second chip 12 are electrically connected to their respective external pins 15 so that they can receive signals from or transmit signals to their respective external pins 15. As marked by ‘A’ of FIG. 2, a signal may be directly transmitted from an external pin 15 to one of the pads of the first chip 11 and then transmitted from the corresponding pad of the first chip 11 to one of the pads of the second chip 12 via a bonding wire 14 connected therebetween. As long as the pads of the first and second chips 11 and 12 receive signals directly from the external pins 15, they are considered as being exposed to an external signal source or destination of the conventional integrated circuit multi-chip package 10, and thus, they should be connected to the static electricity protection circuit, in order to protect the chips 11, 12 from static electricity damage. In order to protect the first and second chips 11 and 12 from static electricity, the conventional integrated circuit multi-chip package 10 may further include a static electricity protection circuit (not shown), which is connected to the pads of the first and second chips 11 and 12, if the pads of the first chip 11 receive signals directly from the external pins 15 and then transmit the received signals to the pads of the second chip 12, as shown in ‘A’ of FIG. 2. This type of multi-chip package structure is disclosed in Korean Patent Publication No. KR1999-0085110.
When testing the conventional integrated circuit multi-chip package 10 having the ‘direct access’ structure described above, it is possible to freely adjust the timing of signals or the level of stress voltage for each of the external pins 15. However, it is difficult to synchronize a signal input to or output from the first chip 11 with a signal input to or output from the second chip 12. In addition, the conventional integrated circuit multi-chip package 10 requires a considerable number of external pins 15 to transmit signals to all of the first and second chips 11 and 12. Moreover, electrostatic defect (ESD)/electric overstress (EOS) tests should be performed on each chip of the conventional integrated circuit multi-chip package 10.